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smsc lan9500/lan9500i revision 1.1 (05-23-08) datasheet datasheet product features lan9500/lan9500i hi-speed usb 2.0 to 10/100 ethernet controller highlights ? single chip hi-speed usb 2.0 to 10/100 ethernet controller ? integrated 10/100 etherne t mac with full-duplex support ? integrated 10/100 ethernet phy with hp auto-mdix support ? integrated usb 2.0 hi-speed device controller ? integrated usb 2.0 hi-speed phy ? implements reduced power operating modes target applications ? embedded systems ? set-top boxes ? pvr?s ? ce devices ? networked printers ? usb port replicators ? standalone usb to ethernet dongles ? test instrumentation ? industrial key benefits ? usb device controller ? fully compliant with hi-speed universal serial bus specification revision 2.0 ? supports hs (480 mbps) and fs (12 mbps) modes ? four endpoints supported ? supports vendor specific commands ? integrated usb 2.0 phy ? remote wakeup supported ? high-performance 10/100 ethernet controller ? fully compliant with ieee802.3/802.3u ? integrated ethernet mac and phy ? 10base-t and 100base-tx support ? full- and half-duplex support ? full- and half-duplex flow control ? preamble generation and removal ? automatic 32-bit crc generation and checking ? automatic payload padding and pad removal ? loop-back modes ? tcp/udp/ip/icmp chec ksum offload support ? flexible address filtering modes ? one 48-bit perfect address ? 64 hash-filtered multicast addresses ? pass all multicast ? promiscuous mode ? inverse filtering ? pass all incoming with status report ? wakeup packet support ? integrated ethernet phy ? auto-negotiation ? automatic polarity detection and correction ? hp auto-mdix support ? link status change wake-up detection ? support for 3 status leds ? external mii to support homepna? and homeplug? phy ? power and i/os ? various low power modes ?11 gpios ? supports bus-powered and self-powered operation ? integrated power-on reset circuit ? external 3.3v i/o supply ? internal 1.8v core supply regulator ? miscellaneous features ? eeprom controller ? ieee 1149.1 (jtag) boundary scan ? requires single 25 mhz crystal ? software ? windows xp/vista driver ? linux driver ? win ce driver ?mac os driver ? eeprom utility ? packaging ? 56-pin qfn (8x8 mm) lead-free rohs compliant package ? environmental ? commercial temperature range (0c to +70c) ? industrial temperature range (-40c to +85c)
hi-speed usb 2.0 to 10/100 ethernet controller datasheet smsc lan9500/lan9500i 2 revision 1.1 (05-23-08) datasheet order number(s): lan9500-abzj for 56-pin, qfn lead-free rohs compliant pa ckage (0 to +70c temp range) LAN9500I-ABZJ for 56-pin, qfn lead-free rohs compliant packag e (-40 to +85c temp range) 80 arkay drive, hauppauge, ny 11788 (631) 435-6000, fax (631) 273-3123 copyright ? 2008 smsc or its subsidiaries. all rights reserved. circuit diagrams and other information relating to smsc produc ts are included as a means of illustrating typical applications. consequently, complete information sufficient for construction purposes is not necessarily given. although the information has been checked and is believed to be accurate, no re sponsibility is assumed for inaccuracies. smsc reserves the right to make changes to specifications and produc t descriptions at any time without notice. contact your local sm sc sales office to obtain the latest specifications before placing your product order. the provision of this inform ation does not convey to the purchaser of the described semicond uctor devices any licenses under any patent rights or other intellectual property rights of smsc or others. all sales are expressly conditional on your agreement to the te rms and conditions of the most recently dated version of smsc's standard terms of sale agreement dated before the date of your order (the "terms of sale agreement"). the pro duct may contain design defects or errors known as anomalies which may cause the product's functions to deviate from published specifications. anomaly sheets are availab le upon request. smsc products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property damage. any and all such uses without prior written approval of an officer of smsc and further testing and/or modification will be fully at the risk of the customer. copies of this document or other smsc literature, as well as the terms of sale agreement, may be obtained by visiting smsc?s website at h ttp://www.smsc.com. smsc is a registered trademark of standard microsystems corporat ion (?smsc?). product names and company na mes are the trademarks of their respective holders. smsc disclaims and excludes any and all warranties, including without limitation any and all implied warranties of merchantabil ity, fitness for a particular purpose, title, and against infringement and the like, and any and all warranties arising from any cou rse of dealing or usage of trade. in no event shall smsc be liable for any direct, incidental, indirect, special, punitive, or cons equential damages; or for lost data, profits, savings or revenues of any kind; regardless of the form of action, whether based on contrac t; tort; negligence of smsc or others; strict liability; breach of warranty; or otherwise; whether or not any remedy of buyer is h eld to have failed of its essential purpose, and whether or no t smsc has been advised of the possibility of such damages.
hi-speed usb 2.0 to 10/100 ethernet controller datasheet smsc lan9500/lan9500i 3 revision 1.1 (05-23-08) datasheet table of contents chapter 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1.2 usb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1.3 fifo controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1.4 ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1.5 power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1.6 eeprom controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.1.7 general purpose i/o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 chapter 2 pin description and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1 buffer types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 chapter 3 operational characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.1 absolute maximum ratings*. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.2 operating conditions** . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.3 power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.3.1 suspend2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.3.2 maximum power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.4 dc specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.5 ac specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.5.1 equivalent test load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.5.2 power-on configuration strap valid timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.5.3 reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.5.4 eeprom timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.6 clock circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 chapter 4 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
hi-speed usb 2.0 to 10/100 ethernet controller datasheet revision 1.1 (05-23-08) 4 smsc lan9500/lan9500i datasheet list of figures figure 1.1 lan9500/lan9500i system diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2.1 lan9500/lan9500i 56-q fn pin assignments (top view). . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 3.1 output equivalent test load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 3.2 power-on configuration strap valid timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 3.3 eeprom timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 4.1 lan9500/lan9500i 56-qfn package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 4.2 lan9500/lan9500i 56-qfn re commended pcb land pattern . . . . . . . . . . . . . . . . . . . . . 30
hi-speed usb 2.0 to 10/100 ethernet controller datasheet smsc lan9500/lan9500i 5 revision 1.1 (05-23-08) datasheet list of tables table 2.1 mii interface pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 2.2 eeprom pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 2.3 jtag pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 2.4 miscellaneous pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 2.5 usb pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 2.6 ethernet phy pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 2.7 i/o power pins, core power pins, and ground pad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 2.8 no-connect pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 2.9 56-qfn package pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 2.10 buffer types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 3.1 suspend2 - supply and current (typical) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 3.2 maximum power consumption - supply and current (maximum). . . . . . . . . . . . . . . . . . . . . . 22 table 3.3 i/o buffer characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 3.4 100base-tx transceiver ch aracteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 table 3.5 10base-t transceiver char acteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 3.6 power-on configuration st rap valid timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 table 3.7 eeprom timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 3.8 lan9500/lan9500i crystal specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 8 table 4.1 lan9500/lan9500i 56-qfn dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
hi-speed usb 2.0 to 10/100 ethernet controller datasheet revision 1.1 (05-23-08) 6 smsc lan9500/lan9500i datasheet chapter 1 introduction 1.1 block diagram 1.1.1 overview the lan9500/lan9500i is a high performance hi-s peed usb 2.0 to 10/100 ethernet controller. with applications ranging from embedde d systems, set-top boxes, and pvr?s , to usb port replicators, usb to ethernet dongles, and test instrumentation, th e lan9500/lan9500i is a high performance and cost competitive usb to ethernet connectivity solution. the lan9500/lan9500i contains an integrated 10 /100 ethernet phy, usb phy, hi-speed usb 2.0 device controller, 10/100 ethernet mac, tap controller, eeprom cont roller, and a fifo controller with a total of 30 kb of internal packet buffering. the internal usb 2.0 device controller and usb phy are compliant with the usb 2.0 hi-speed standard. the lan9500/lan9500i implements control, interrupt, bulk-in, and bulk-out usb endpoints. the ethernet controller supports auto-negotiation, auto-polarity correction, hp auto-mdix, and is compliant with the ieee 80 2.3 and ieee 802.3u standards. an exte rnal mii interface provides support for an external fast ethernet phy, homepna, and homeplug functionality. multiple power management feat ures are provided, including various low power modes and "magic packet", "wake on lan", and "link status c hange" wake events. these wake events can be programmed to initiate a usb remote wakeup. an internal eeprom controller exis ts to load various usb configur ation informati on and the device mac address. the integrated ieee 11 49.1 compliant tap controller provides boundar y scan via jtag. figure 1.1 lan9500/lan9500i system diagram tap controller eeprom controller usb 2.0 device controller sram ethernet phy 10/100 ethernet mac fifo controller usb phy lan9500/lan9500i mii: to optional external phy ethernet eeprom jtag usb
hi-speed usb 2.0 to 10/100 ethernet controller datasheet smsc lan9500/lan9500i 7 revision 1.1 (05-23-08) datasheet 1.1.2 usb the usb portion of the lan9500/lan9500i integrates a hi-speed usb 2.0 device controller and usb phy. the usb device controller contains a usb low-level protocol interpreter which implements the usb bus protocol, packet generation/ex traction, pid/device id parsing, and crc coding/decoding, with autonomous error handling. the usb device controller is capable of operating in usb 2.0 hi-speed and full-speed compliant modes and contains aut onomous protocol handling functions such as handling of suspend/resume/reset conditions, remo te wakeup, and stall condition clearing on setup packets. the usb device controller also autonomously handles error conditions such as retry for crc and data toggle errors, and generates nyet, stall, ack and nack handshake responses, depending on the endpoint buffer status. the lan9500/lan9500i implements four usb endpoints: control, interrupt, bulk-in, and bulk-out. the bulk-in and bulk-out endpoints allow for ethernet reception and transmission respectively. implementation of vendor-specific commands allows fo r efficient statistics gathering and access to the lan9500/lan9500i system control and status registers. 1.1.3 fifo controller the fifo controller uses an internal sram to buffer rx and tx traffic. bulk-out packets from the usb controller are directly stored into the tx buffer. et hernet frames are directly stored into the rx buffer and become the basis for bulk-in packets. 1.1.4 ethernet the lan9500/lan9500i integrates an ieee 802.3 ph y for twisted pair ethernet applications and a 10/100 ethernet media access controller (mac). the phy can be configured for either 100 mbps (100base-tx) or 10 mbps (10base-t) ethernet operation in either full- or half-duplex configur ations and includes auto-negotiation, auto-polarity correction, and auto-mdix. minimal external co mponents are required for the utilization of the integrated phy. optionally, an external phy may be used via the m ii (media independent interface) port, effectively bypassing the internal phy. this option allows support for homepna and homeplug applications. the ethernet mac/phy supports numerous power management wakeup features, including ?magic packet?, ?wake on lan?, and ?link status change?. 1.1.5 power management the lan9500/lan9500i features th ree variations of usb suspen d: suspend0, suspend1, and suspend2. these modes allow the application to select the ideal balance of remote wakeup functionality and power consumption. ? suspend0: supports gpio, ?wake on lan?, and ?magic packet? remote wakeup events. this suspend state reduces power by stopping the clocks of the mac and other internal modules. ? suspend1: supports gpio and ?link status change? for remote wakeup events. this suspend state consumes less power than suspend0. ? suspend2: supports only gpio assertion for a remote wakeup event. this suspend state consumes less than 1 ma. this is the default suspend mode for the lan9500/lan9500i.
hi-speed usb 2.0 to 10/100 ethernet controller datasheet revision 1.1 (05-23-08) 8 smsc lan9500/lan9500i datasheet 1.1.6 eeprom controller the lan9500/lan9500i contains an eeprom controller for connection to an external eeprom. this allows for the automatic loading of static configuration data upon power-on reset, pin reset, or software reset. the eeprom can be configured to load usb descriptors, usb device configuration, and mac address. 1.1.7 general purpose i/o when configured for internal phy mode, up to el even gpios are supported. all gpios can serve as remote wakeup events when the lan9500/lan9500i is in a suspended state.
hi-speed usb 2.0 to 10/100 ethernet controller datasheet smsc lan9500/lan9500i 9 revision 1.1 (05-23-08) datasheet chapter 2 pin description and configuration figure 2.1 lan9500/lan9500i 56-qfn pin assignments (top view) vss note: exposed pad (vss) on bottom of package must be connected to ground note: when hp auto-mdix is activated, the txn/txp pins can function as rxn/rxp and vice-versa smsc lan9500/lan9500i 56 pin qfn (top view) txen rxdv nspd_led/gpio10 nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 42 41 40 39 38 37 36 35 34 33 32 31 30 29 56 55 54 53 52 51 50 49 48 47 46 45 44 43 test2 usbdp usbdm vdd18pll vdd33a exres vdd33a rxp rxn vdd33a txp txn nphy_int rxclk/rmt_wkp tdi/rxd3 tms/rxd2 tck/rxd1 tdo/nphy_rst ntrst/rxd0 vdd33io phy_sel nc eedi/port_swap eedo/automdix_en eecs eeclk/pwr_sel rxer/eep_disable crs/gpio3 col/gpio0 txclk/eep_size vdd33io test1 vdd18core vdd33io vdd33io txd3/gpio7 txd2/gpio6 txd1/gpio5 txd0/gpio4 nlnka_led/gpio9 nfdx_led/gpio8 vdd33io nreset mdio/gpio1 mdc/gpio2 vdd18core vbus_det xo xi vdd18usbpll usbrbias vdd33a
hi-speed usb 2.0 to 10/100 ethernet controller datasheet revision 1.1 (05-23-08) 10 smsc lan9500/lan9500i datasheet table 2.1 mii interface pins num pins name symbol buffer type description 1 receive error (internal phy mode) rxer o8 (pd) receive error: in internal phy mode, this pin can be configured to display the respective internal mii signal. receive error (external phy mode) rxer is (pd) receive error: in external phy mode, the signal on this pin is input from the external phy and indicates a receive error in the packet. eeprom disable configuration strap eep_disable is (pd) eeprom disable configuration strap: this strap disables the autol oading of the eeprom contents. the assertion of this strap does not prevent register access to the eeprom. 0 = eeprom is recognized if present. 1 = eeprom is not recognized even if it is present. see note 2.1 for more information on configuration straps. 1 transmit enable (internal phy mode) txen o8 transmit enable: in internal phy mode, this pin can be configured to display the respective internal mii signal. transmit enable (external phy mode) txen o8 (pd) transmit enable: in external phy mode, this pin output to the external phy and indicates valid data on txd[3:0]. 1 receive data valid (internal phy mode) rxdv o8 receive data valid: in internal phy mode, this pin can be configured to display the respective internal mii signal. receive data valid (external phy mode) rxdv is (pd) receive data valid: in external phy mode, the signal on this pin is input from the external phy and indicates valid data on rxd[3:0]. 1 receive clock (internal phy mode) rxclk o8 (pd) receive clock: in internal phy mode, this pin can be configured to display the respective internal mii signal. receive clock (external phy mode) rxclk is (pd) receive clock: in external phy mode, this pin is the receiver clock input from the external phy. remote wakeup configuration strap rmt_wkp is (pd) remote wakeup configuration strap: this strap configures the default descriptor values to support remote wakeup. 0 = remote wakeup is not supported. 1 = remote wakeup is supported. see note 2.1 for more information on configuration straps.
hi-speed usb 2.0 to 10/100 ethernet controller datasheet smsc lan9500/lan9500i 11 revision 1.1 (05-23-08) datasheet 1 carrier sense (internal phy mode) crs o8 (pu) carrier sense: in internal phy mode, this pin can be configured to display the respective internal mii signal. carrier sense (external phy mode) crs is (pd) carrier sense: in external phy mode, the signal on this pin is input from the external phy and indicates a network carrier. general purpose i/o 3 (internal phy mode only) gpio3 is/o8/ od8 (pu) general purpose i/o 3 1 mii collision detect (internal phy mode) col o8 (pu) mii collision detect: in internal phy mode, this pin can be configured to display the respective internal mii signal. mii collision detect (external phy mode) col is (pd) mii collision detect: in external phy mode, the signal on this pin is input from the external phy and indicates a collision event. general purpose i/o 0 (internal phy mode only) gpio0 is/o8/ od8 (pu) general purpose i/o 0 1 management data (internal phy mode) mdio o8 (pu) management data: in internal phy mode, this pin can be configured to display the respective internal mii signal. management data (external phy mode) mdio is/o8 (pd) management data: in external phy mode, this pin provides the management data to/from the external phy. general purpose i/o 1 (internal phy mode only) gpio1 is/o8/ od8 (pu) general purpose i/o 1 1 management clock (internal phy mode) mdc o8 (pu) management clock: in internal ph y mode, this pin can be configured to display the respective internal mii signal. management clock (external phy mode) mdc o8 (pd) management clock: in external phy mode, this pin outputs the management clock to the external phy. general purpose i/o 2 (internal phy mode only) gpio2 is/o8/ od8 (pu) general purpose i/o 2 table 2.1 mii interfa ce pins (continued) num pins name symbol buffer type description
hi-speed usb 2.0 to 10/100 ethernet controller datasheet revision 1.1 (05-23-08) 12 smsc lan9500/lan9500i datasheet 1 transmit data 3 (internal phy mode) txd3 o8 (pu) transmit data 3: in internal phy mode, this pin can be configured to display the respective internal mii signal. transmit data 3 (external phy mode) txd3 o8 (pd) transmit data 3: in external phy mode, this pin functions as the transmit data 3 output to the external phy. general purpose i/o 7 (internal phy mode only) gpio7 is/o8/ od8 (pu) general purpose i/o 7 1 transmit data 2 (internal phy mode) txd2 o8 (pu) transmit data 2: in internal phy mode, this pin can be configured to display the respective internal mii signal. transmit data 2 (external phy mode) txd2 o8 (pd) transmit data 2: in external phy mode, this pin functions as the transmit data 2 output to the external phy. general purpose i/o 6 (internal phy mode only) gpio6 is/o8/ od8 (pu) general purpose i/o 6 1 transmit data 1 (internal phy mode) txd1 o8 (pu) transmit data 1: in internal phy mode, this pin can be configured to display the respective internal mii signal. transmit data 1 (external phy mode) txd1 o8 (pd) transmit data 1: in external phy mode, this pin functions as the transmit data 1 output to the external phy. general purpose i/o 5 (internal phy mode only) gpio5 is/o8/ od8 (pu) general purpose i/o 5 1 transmit data 0 (internal phy mode) txd0 o8 (pu) transmit data 0: in internal phy mode, this pin can be configured to display the respective internal mii signal. transmit data 0 (external phy mode) txd0 o8 (pd) transmit data 0: in external phy mode, this pin functions as the transmit data 0 output to the external phy. general purpose i/o 4 (internal phy mode only) gpio4 is/o8/ od8 (pu) general purpose i/o 4 table 2.1 mii interfa ce pins (continued) num pins name symbol buffer type description
hi-speed usb 2.0 to 10/100 ethernet controller datasheet smsc lan9500/lan9500i 13 revision 1.1 (05-23-08) datasheet note 2.1 configuration strap values are latched on power-on reset. configuration straps are identified by an underlined symbol name. signals that function as configuration straps must be augmented with an external resistor when connected to a load. 1 transmit clock (internal phy mode) txclk o8 (pu) transmit clock: in internal phy mode, this pin can be configured to display the respective internal mii signal. transmit clock (external phy mode) txclk is (pu) transmit clock: in external phy mode, this pin is the transmitter clock input from the external phy. eeprom size configuration strap eep_size is (pu) eeprom size: the eep_size strap selects the size of the eeprom attached to the lan9500/lan9500i. 0 = 128 byte eeprom is attached and a total of seven address bits are used. 1 = 256/512 byte eeprom is attached and a total of nine address bits are used. see note 2.1 for more information on configuration straps. table 2.2 eeprom pins num pins name symbol buffer type description 1 eeprom data in eedi is (pd) eeprom data in: this pin is driven by the eedo output of th e external eeprom. usb port swap configuration strap port_swap is (pd) usb port swap configuration strap: swaps the mapping of usbdp and usbdm. 0 = usbdp maps to the usb d+ line and usbdm maps to the usb d- line. 1 = usbdp maps to the usb d- line. usbdm maps to the usb d+ line. see note 2.2 for more information on configuration straps. 1 eeprom data out eedo o8 (pu) eeprom data out: this pin drives the eedi input of the external eeprom. auto-mdix enable configuration strap automdix_en is (pu) auto-mdix enable configuration strap: determines the default auto-mdix setting. 0 = auto-mdix is disabled. 1 = auto-mdix is enabled. see note 2.2 for more information on configuration straps. table 2.1 mii interfa ce pins (continued) num pins name symbol buffer type description
hi-speed usb 2.0 to 10/100 ethernet controller datasheet revision 1.1 (05-23-08) 14 smsc lan9500/lan9500i datasheet note 2.2 configuration strap values are latched on power-on reset. configuration straps are identified by an underlined symbol name. signals that function as configuration straps must be augmented with an external resistor when connected to a load. 1 eeprom chip select eecs o8 eeprom chip select: this pin drives the chip select output of the external eeprom. 1 eeprom clock eeclk o8 (pd) eeprom clock: this pin drives the eeprom clock of the external eeprom. power select configuration strap pwr_sel is (pd) power select configuration strap: determines the default power setting when no eeprom is present. 0 = the lan9500/lan9500i is bus powered. 1 = the lan9500/lan9500i is self powered. see note 2.2 for more information on configuration straps. table 2.3 jtag pins num pins name symbol buffer type description 1 jtag test port reset (internal phy mode) ntrst is (pu) jtag test port reset (active-low): in internal phy mode, this pin functions as the jtag test port reset input. receive data 0 (external phy mode) rxd0 is (pd) receive data 0: in external phy mode, this pin functions as the receive data 0 input from the external phy. 1 jtag test data out (internal phy mode) tdo o8 jtag data output: in internal phy mode, this pin functions as the jtag data output. phy reset (external phy mode) nphy_rst o8 phy reset (active-low): in external phy mode, this pin functions as the phy reset output. 1 jtag test clock (internal phy mode) tck is (pu) jtag test clock: in internal phy mode, this pin functions as the jtag test clock. the maximum operating frequency of this clock is 25mhz. receive data 1 (external phy mode) rxd1 is (pd) receive data 1: in external phy mode, this signal functions as the receive data 1 input from the external phy. table 2.2 eeprom pins (continued) num pins name symbol buffer type description
hi-speed usb 2.0 to 10/100 ethernet controller datasheet smsc lan9500/lan9500i 15 revision 1.1 (05-23-08) datasheet 1 jtag test mode select (internal phy mode) tms is (pu) jtag test mode select: in internal phy mode, this pin functions as the jtag test mode select. receive data 2 (external phy mode) rxd2 is (pd) receive data 2: in external phy mode, this signal functions as the receive data 2 input from the external phy. 1 jtag test data input (internal phy mode) tdi is (pu) jtag data input: when in internal phy mode, this pin functions as the jtag data input. receive data 3 (external phy mode) rxd3 is (pd) receive data 3: in external phy mode, this pin functions as the receive data 3 input from the external phy. table 2.4 miscellaneous pins num pins name symbol buffer type description 1 phy select phy_sel is (pd) phy select: selects whether to use the internal ethernet phy or the external phy connected to the mii port. 0 = internal phy is used. 1 = external phy is used. 1 system reset nreset is (pu) system reset (active-low) 1 ethernet full-duplex indicator led nfdx_led od12 (pu) ethernet full-duplex indicator led (active- low): this signal is driven low (led on) when the ethernet link is operating in full-duplex mode. general purpose i/o 8 gpio8 is/o12/ od12 (pu) general purpose i/o 8 1 ethernet link activity indicator led nlnka_led od12 (pu) ethernet link activity indicator led (active- low): this signal is driven low (led on) when a valid link is detected. this pin is pulsed high (led off) for 80ms whenever transmit or receive activity is detected. this pin is then driven low again for a minimum of 80ms, after which time it will repeat the process if tx or rx activity is detected. effectively, led2 is activated solid for a link. when transmit or receive activity is sensed, led2 will function as an activity indicator. general purpose i/o 9 gpio9 is/o12/ od12 (pu) general purpose i/o 9 table 2.3 jtag pins (continued) num pins name symbol buffer type description
hi-speed usb 2.0 to 10/100 ethernet controller datasheet revision 1.1 (05-23-08) 16 smsc lan9500/lan9500i datasheet 1 ethernet speed indicator led nspd_led od12 (pu) ethernet speed indicator led (active-low): this pin is driven low (led on) when the ethernet operating speed is 100mbs, or during auto- negotiation. this pin is driven high during 10mbs operation, or during line isolation. general purpose i/o 10 gpio10 is/o12/ od12 (pu) general purpose i/o 10 1 detect upstream vbus power vbus_det is_5v (pd) detect upstream vbus power: detects state of upstream bus power. this pin must be tied to vdd33io when operating in bus powered mode. 1 test 1 test1 ai test 1: this pin must always be connected to vdd33io for proper operation. 1 test 2 test2 ai test 2: this pin must always be connected to vss for proper operation. table 2.5 usb pins num pins name symbol buffer type description 1 usb dminus usbdm aio usb dminus note: the functionality of this pin may be swapped to usb dplus via the port_swap configuration strap. 1 usb dplus usbdp aio usb dplus note: the functionality of this pin may be swapped to usb dminus via the port_swap configuration strap. 1 external usb bias resistor. usbrbias ai external usb bias resistor: used for setting hs transmit current level and on-chip termination impedance. connect to an external 12k 1.0% resistor to ground. 1 usb pll +1.8v supply vdd18usbpll p usb pll +1.8v supply: this pin must be connected to vdd18core for proper operation. refer to the lan9500/lan9500i reference schematic for additional connection information. 1 crystal input xi iclk crystal input: external 25 mhz crystal input. note: this signal can also be driven by a single-ended clock oscillator. when this method is used, xo should be left unconnected 1 crystal output xo oclk crystal output: external 25 mhz crystal output. table 2.4 miscellaneous pins (continued) num pins name symbol buffer type description
hi-speed usb 2.0 to 10/100 ethernet controller datasheet smsc lan9500/lan9500i 17 revision 1.1 (05-23-08) datasheet table 2.6 ethernet phy pins num pins name symbol buffer type description 1 ethernet tx data out negative txn aio ethernet transmit data out negative: the transmit data outputs may be swapped internally with receive data inputs when auto-mdix is enabled. 1 ethernet tx data out positive txp aio ethernet transmit data out positive: the transmit data outputs may be swapped internally with receive data inputs when auto-mdix is enabled. 1 ethernet rx data in negative rxn aio ethernet receive data in negative: the receive data inputs may be swapped internally with transmit data outputs when auto-mdix is enabled. 1 ethernet rx data in positive rxp aio ethernet receive data in positive: the receive data inputs may be swapped internally with transmit data outputs when auto-mdix is enabled. 1 phy interrupt (internal phy mode) nphy_int o8 phy interrupt (active-low): in internal phy mode, this signal can be configured to output the internal phy interrupt signal. note: the internal phy interrupt signal is active-high. phy interrupt (external phy mode) nphy_int is_5v (pu) phy interrupt (active-low): in external phy mode, the signal on this pin is input from the external phy and indicates a phy interrupt has occurred. 4 +3.3v analog power supply vdd33a p +3.3v analog power supply refer to the lan9500/lan9500i reference schematic for connection information. 1 external phy bias resistor exres ai external phy bias resistor: used for the internal bias circuits. connect to an external 12.4k 1.0% resistor to ground. 1 ethernet pll +1.8v power supply vdd18pll p ethernet pll +1.8 v power supply: this pin must be connected to vdd18core for proper operation. refer to the lan9500/lan9500i reference schematic for additional connection information.
hi-speed usb 2.0 to 10/100 ethernet controller datasheet revision 1.1 (05-23-08) 18 smsc lan9500/lan9500i datasheet table 2.7 i/o power pins, core power pins, and ground pad num pins name symbol buffer type description 5 +3.3v i/o power vdd33io p +3.3v power supp ly for i/o pins refer to the lan9500/lan9500i reference schematic for connection information. 2 digital core +1.8v power supply output vdd18core p digital core +1.8v power supply output refer to the lan9500/lan9500i reference schematic for connection information. exposed pad on package bottom ( figure 2.1 ) ground vss p common ground table 2.8 no-connect pins 56-qfn pin name symbol buffer type description 2 no connect nc - no connect: these pins must be left floating for normal device operation
hi-speed usb 2.0 to 10/100 ethernet controller datasheet smsc lan9500/lan9500i 19 revision 1.1 (05-23-08) datasheet table 2.9 56-qfn package pin assignments pin num pin name pin num pin name pin num pin name pin num pin name 1 nphy_int 15 vdd33a 29 eeclk/pwr_sel 43 txen 2 txn 16 usbrbias 30 eecs 44 rxer/eep_disable 3 txp 17 vdd18usbpll 31 eedo/automdix_en 45 crs/gpio3 4 vdd33a 18 xi 32 eedi/port_swap 46 col/gpio0 5 rxn 19 xo 33 nc 47 txclk/eep_size 6 rxp 20 vbus_det 34 phy_sel 48 vdd33io 7 vdd33a 21 vdd18core 35 vdd33io 49 test1 8 exres 22 mdc/gpio2 36 ntrst/rxd0 50 vdd18core 9 vdd33a 23 mdio/gpio1 37 td o/nphy_rst 51 vdd33io 10 vdd18pll 24 nreset 38 tck/rxd1 52 vdd33io 11 usbdm 25 vdd33io 39 tms/rxd2 53 txd3/gpio7 12 usbdp 26 nfdx_led/gpio8 40 tdi/rxd3 54 txd2/gpio6 13 test2 27 nlnka_led/gpio9 41 rxclk/rmt_wkp 55 txd1/gpio5 14 nc 28 nspd_led/gpio10 42 rxdv 56 txd0/gpio4 exposed pad must be connected to vss
hi-speed usb 2.0 to 10/100 ethernet controller datasheet revision 1.1 (05-23-08) 20 smsc lan9500/lan9500i datasheet 2.1 buffer types table 2.10 buffer types buffer type description is schmitt-triggered input is_5v 5v tolerant schmitt-triggered input o8 output with 8ma sink and 8ma source od8 open-drain output with 8ma sink o12 output with 12ma sink and 12ma source od12 open-drain output with 12ma sink pu 50ua (typical) internal pull-up. unless otherwis e noted in the pin description, internal pull- ups are always enabled. note: internal pull-up resistors prevent unconnected inputs from floating. do not rely on internal resistors to drive signals external to the lan9500/lan9500i. when connected to a load that must be pulled high, an external resistor must be added. pd 50ua (typical) internal pull-down. unless ot herwise noted in the pin description, internal pull-downs are always enabled. note: internal pull-down resistors prevent unconnected inputs from floating. do not rely on internal resistors to drive signals external to the lan9500/lan9500i. when connected to a load that must be pulled low, an external resistor must be added. ai analog input aio analog bi-directional iclk crystal oscillator input pin oclk crystal oscillator output pin p power pin
hi-speed usb 2.0 to 10/100 ethernet controller datasheet smsc lan9500/lan9500i 21 revision 1.1 (05-23-08) datasheet chapter 3 operational characteristics 3.1 absolute maximum ratings* supply voltage (vdd33io, vdd33a) ( note 3.1 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0v to +3.6v positive voltage on signal pins, with respect to ground ( note 3.2 ). . . . . . . . . . . . . . . . . . . . . . . . . . +6v negative voltage on signal pins, with respect to ground ( note 3.3 ) . . . . . . . . . . . . . . . . . . . . . . . . -0.5v positive voltage on xi, with respect to ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+ 4.6v positive voltage on xo, with re spect to ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+2. 5v ambient operating temperature in still air (t a ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . note 3.4 storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55 o c to +150 o c lead temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . refer to jedec spec. j-std-020 hbm esd performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .tbd note 3.1 when powering this device from laboratory or system power su pplies, it is important that the absolute maximum ratings not be exceeded or device failure can result. some power supplies exhibit voltage spikes on their outputs when ac power is switched on or off. in addition, voltage transients on the ac power line may appear on the dc output. if this possibility exists, it is suggeste d that a clamp circuit be used. note 3.2 this rating does not apply to the following pins: xi, xo, exres, usbrbias. note 3.3 this rating does not apply to the following pins: exres, usbrbias. note 3.4 0 o c to +70 o c for commercial version, -40 o c to +85 o c for industrial version. *stresses exceeding those listed in this section c ould cause permanent damage to the device. this is a stress rating only. exposure to absolute maximum rating conditions for extended periods may affect device reliability. functional operation of the device at any condition exceeding those indicated in section 3.2, "operating conditions**" , section 3.4, "dc specifications" , or any other applicable section of this specification is not im plied. note, device signals are not 5 volt tolerant unless specified otherwise. 3.2 operating conditions** supply voltage (vdd33a, vdd33bias, vdd33io) . . . . . . . . . . . . . . . . . . . . . . . . . . .+3.3v +/- 300mv ambient operating temperature in still air (t a ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . note 3.4 **proper operation of lan9500/lan9500i is guaranteed only within the ranges specified in this section.
hi-speed usb 2.0 to 10/100 ethernet controller datasheet revision 1.1 (05-23-08) 22 smsc lan9500/lan9500i datasheet 3.3 power consumption this section details the power consumption of lan9500/ lan9500i as measured during various modes of operation. power consumption val ues are provided for both the device-only, and for the device plus ethernet components. power dissipation is determined by temperature, supply voltage, and external source/sink requirements. 3.3.1 suspend2 note: suspend2 power numbers measured while bus powered 3.3.2 maximum power consumption note 3.5 over the conditions specified in section 3.2, "operating conditions**" . table 3.1 suspend2 - supply and current (typical) parameter typical (@ 3.3v) unit 100base-tx full duplex supply current (vdd33io, vdd33a) <1 ma power dissipation (device only) tbd mw power dissipation (device and ethernet components) tbd mw ambient operating temperature in still air (t a )25 o c 10base-t full duplex supply current (vdd33io, vdd33a) tbd ma power dissipation (device only) tbd mw power dissipation (device and ethernet components) tbd mw ambient operating temperature in still air (t a )25 o c table 3.2 maximum power consumption - supply and current (maximum) parameter maximum (@ 3.6v) unit 100base-tx full duplex supply current (vdd33io, vdd33a) tbd ma power dissipation (device only) tbd mw power dissipation (device and ethernet components) tbd mw ambient operating temperature in still air (t a ) note 3.5 o c 10base-t full duplex supply current (vdd33io, vdd33a) tbd ma power dissipation (device only) tbd mw power dissipation (device and ethernet components) tbd mw ambient operating temperature in still air (t a ) note 3.5 o c
hi-speed usb 2.0 to 10/100 ethernet controller datasheet smsc lan9500/lan9500i 23 revision 1.1 (05-23-08) datasheet 3.4 dc specifications note 3.6 this specification applies to all inputs and tri-stated bi-directional pins. internal pull-down and pull-up resistors add +/- 50ua per-pin (typical). table 3.3 i/o buffer characteristics parameter symbol min typ max units notes is type input buffer low input level high input level negative-going threshold positive-going threshold schmitttrigger hysteresis (v iht - v ilt ) input leakage (v in = vss or vdd33io) input capacitance v ili v ihi v ilt v iht v hys i ih c in -0.3 1.01 1.39 345 tbd 1.18 1.6 420 3.6 1.35 1.8 485 tbd tbd v v v v mv ua pf schmitt trigger schmitt trigger note 3.6 is_5v type input buffer low input level high input level negative-going threshold positive-going threshold schmitttrigger hysteresis (v iht - v ilt ) input leakage (v in = vss or vdd33io) input leakage (v in = 5.5v) input capacitance v ili v ihi v ilt v iht v hys i ih i ih c in -0.3 1.01 1.39 345 tbd 1.18 1.6 420 5.5 1.35 1.8 485 tbd tbd tbd v v v v mv ua ua pf schmitt trigger schmitt trigger note 3.6 note 3.6 , note 3.7 o8 type buffers low output level high output level v ol v oh vdd33io - 0.4 0.4 v v i ol = 8ma i oh = -8ma od8 type buffer low output level v ol 0.4 v i ol = 8ma o12 type buffers low output level high output level v ol v oh vdd33io - 0.4 0.4 v v i ol = 12ma i oh = -12ma od12 type buffer low output level v ol 0.4 v i ol = 12ma iclk type buffer (xi input) low input level high input level v ili v ihi -0.3 1.4 0.5 3.6 v v note 3.8
hi-speed usb 2.0 to 10/100 ethernet controller datasheet revision 1.1 (05-23-08) 24 smsc lan9500/lan9500i datasheet note 3.7 this is the total 5.5v input leakage for the entire device. this value should be divided by the number of pins driven to 5.5v to calc ulate per-pin leakage. for example, if both 5v tolerant inputs are driven to 5. 5v, the per-pin leakage is tbd/2. note 3.8 xi can optionally be driven from a 25mhz single-ended clock oscillator. note 3.9 measured at line side of transformer, line replaced by 100 (+/- 1%) resistor. note 3.10 offset from 16ns pulse width at 50% of pulse peak. note 3.11 measured differentially. note 3.12 min/max voltages guaranteed as measured with 100 resistive load. table 3.4 100base-tx transceiver characteristics parameter symbol min typ max units notes peak differential output voltage high v pph 950 - 1050 mvpk note 3.9 peak differential output voltage low v ppl -950 - -1050 mvpk note 3.9 signal amplitude symmetry v ss 98 - 102 % note 3.9 signal rise and fall time t rf 3.0 - 5.0 ns note 3.9 rise and fall symmetry t rfs --0.5ns note 3.9 duty cycle distortion d cd 35 50 65 % note 3.10 overshoot and undershoot v os --5% jitter 1.4 ns note 3.11 table 3.5 10base-t transceiver characteristics parameter symbol min typ max units notes transmitter peak differential output voltage v out 2.2 2.5 2.8 v note 3.12 receiver differential squelch threshold v ds 300 420 585 mv
hi-speed usb 2.0 to 10/100 ethernet controller datasheet smsc lan9500/lan9500i 25 revision 1.1 (05-23-08) datasheet 3.5 ac specifications this section details the various ac timing specifications of the lan9500/lan9500i. note: the mii timing adheres to the ieee 802.3 specification. refe r to the ieee 802.3 specification for detailed mii timing information. note: the usbdp and usbdm pin timing adheres to the usb 2.0 specification. refer to the universal serial bus revision 2.0 specification for detailed usb timing information. 3.5.1 equivalent test load output timing specifications assume the 25pf equivalent test load illustrated in figure 3.1 below. figure 3.1 output equivalent test load 25 pf output
hi-speed usb 2.0 to 10/100 ethernet controller datasheet revision 1.1 (05-23-08) 26 smsc lan9500/lan9500i datasheet 3.5.2 power-on configurat ion strap valid timing figure 3.2 illustrates the configuration strap valid timi ng requirement in relation to power-on. in order for valid configuration strap values to be read at power-on, the following timing requirements must be met. 3.5.3 reset timing the nreset pin input assertion time must be a minimum of 1 s. assertion of nreset is not a requirement. however, if used, it must be asserted for the minimum period specified. figure 3.2 power-on configuration strap valid timing table 3.6 power-on configuration strap valid timing symbol description min typ max units t cfg configuration strap valid time 15 ms vdd33io configuration straps t cfg 2.0v
hi-speed usb 2.0 to 10/100 ethernet controller datasheet smsc lan9500/lan9500i 27 revision 1.1 (05-23-08) datasheet 3.5.4 eeprom timing the following specifies the eeprom timing requirements for lan9500/lan9500i: figure 3.3 eeprom timing table 3.7 eeprom timing values symbol description min typ max units t ckcyc eeclk cycle time 1110 1130 ns t ckh eeclk high time 550 570 ns t ckl eeclk low time 550 570 ns t cshckh eecs high before rising edge of eeclk 1070 ns t cklcsl eeclk falling edge to eecs low 30 ns t dvckh eedo valid before rising edge of eeclk 550 ns t ckhdis eedo disable after rising edge eeclk 550 ns t dsckh eedi setup to rising edge of eeclk 90 ns t dhckh eedi hold after rising edge of eeclk 0 ns t ckldis eeclk low to data disable (output) 580 ns t cshdv eedio valid after eecs high (verify) 600 ns t dhcsl eedio hold after eecs low (verify) 0 ns t csl eecs low 1070 ns eeclk eedo eedi eecs t ckldis t cshckh eedi (verify) t ckh t ckl t ckcyc t cklcsl t csl t dvckh t ckhdis t dsckh t dhckh t dhcsl t cshdv
hi-speed usb 2.0 to 10/100 ethernet controller datasheet revision 1.1 (05-23-08) 28 smsc lan9500/lan9500i datasheet 3.6 clock circuit lan9500/lan9500i can accept either a 25mhz cryst al (preferred) or a 25mhz single-ended clock oscillator (+/- 50ppm) input. if the single-ended clock oscillator met hod is implemented, xo should be left unconnected and xi should be driven with a nomin al 0-3.3v clock signal. the input clock duty cycle is 40% minimum, 50% typical and 60% maximum. it is recommended that a crystal utilizing matchi ng parallel load capacitors be used for the crystal input/output signals (xi/xo). see table 3.8 for the recommended cr ystal specifications. note 3.13 the maximum allowable values for frequency tolerance and frequency stability are application dependant. since any particular application must meet the ieee +/-50 ppm total ppm budget, the combination of these tw o values must be approximately +/-45 ppm (allowing for aging). note 3.14 frequency deviation over time is also referred to as aging. note 3.15 the total deviation for the transmitter clock frequency is specified by ieee 802.3u as +/- 50 ppm. note 3.16 0 o c for commercial version, -40 o c for industrial version. note 3.17 +70 o c for commercial version, +85 o c for industrial version. note 3.18 this number includes the pad, the bond wire and the lead frame. pcb capacitance is not included in this value. the xo/xi pin and pcb capacitance values are required to accurately calculate the value of the two exte rnal load capacitors. these two external load capacitors determine the accuracy of the 25.000 mhz frequency. table 3.8 lan9500/lan9500i crystal specifications parameter symbol min nom max units notes crystal cut at, typ crystal oscillation mode fundamental mode crystal calibration mode parallel resonant mode frequency f fund - 25.000 - mhz frequency tolerance @ 25 o cf tol - - +/-50 ppm note 3.13 frequency stability over temp f temp - - +/-50 ppm note 3.13 frequency deviation over time f age - +/-3 to 5 - ppm note 3.14 total allowable ppm budget - - +/-50 ppm note 3.15 shunt capacitance c o -7 typ-pf load capacitance c l - 20 typ - pf drive level p w 0.5 - - mw equivalent series resistance r 1 --30ohm operating temperature range note 3.16 - note 3.17 o c lan9500/lan9500i xi pin capacitance -3 typ-pf note 3.18 lan9500/lan9500i xo pin capacitance -3 typ-pf note 3.18
hi-speed usb 2.0 to 10/100 ethernet controller datasheet smsc lan9500/lan9500i 29 revision 1.1 (05-23-08) datasheet chapter 4 package outline notes: 1. all dimensions are in mill imeters unless otherwise noted. 2. position tolerance of each terminal and exposed pad is +/- 0.05 mm at maxi mum material condition. dimension ?b? applies to plated terminals and is measured between 0.15 and 0.30 mm from the terminal tip. 3. the pin 1 identifier may vary, but is always located within the zone indicated. figure 4.1 lan9500/lan9500i 56-qfn package table 4.1 lan9500/lan9500i 56-qfn dimensions min nominal max remarks a 0.70 - 1.00 overall package height a1 0.00 0.02 0.05 standoff a2 - - 0.90 mold cap thickness d/e 7.85 8.00 8.15 x/y body size d1/e1 7.55 - 7.95 x/y mold cap size d2/e2 5.75 5.90 6.05 x/y exposed pad size l 0.30 - 0.50 terminal length b 0.18 0.25 0.30 terminal width e 0.50 bsc terminal pitch
hi-speed usb 2.0 to 10/100 ethernet controller datasheet revision 1.1 (05-23-08) 30 smsc lan9500/lan9500i datasheet figure 4.2 lan9500/lan9500i 56-qfn recommended pcb land pattern

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